搜索资源列表
rs-5-3
- 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
RSdecoder.rar
- cpld/fpga RS(204,188)译码器的verilog程序,cpld/fpga RS (204,188) decoder of the Verilog program
rs_decoder_31_19_6_latest.tar.
- RS解码器的FPGA实现，有TestBench,RS decoder FPGA to achieve, there TestBench
final_decode
- rs解码器在fpga上的实现，采用的modelsim开发平台 -rs on fpga decoder in the realization of the development platform used in modelsim
learn_RS_coding
- 自己根据网上已有程序改写的(127,115)RS编码，有详细的注释及对FPGA实现算法的改写(参考try123.m)，希望可以让大家少走弯路-(127,115) rs encoder/decorder with detailed annotations.
rs_encorder
- RS编码的fpga实现，详细的vhdl文档，可以硬件实现。-RS coding fpga implementation, detailed documentation of vhdl can be implemented by hardware.
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
rs
- rs编解码，对实现了rs码的编解码，并对其误码率进行了分析仿真-rs codec, to the achievement of the rs code coding and decoding, and BER analysis simulation
uarts
- RS-232 interface example for FPGA/EDA developers
rs-codec(255-223)
- RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
RS_Verilog
- RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
rscode
- RS编码器在fpga上的实现，用的modelsim开发环境-RS encoder in the realization of the fpga, development environment used in modelsim
rs_encoder
- RS编码器的fpga实现，有TESTBench-RS encoder to achieve the fpga, and TESTBench
rs_5_3_gf256_latest.tar
- this paper deal with rs decoder algorithm-this paper deal with rs decoder algorithm
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
RS-decode_base-on-FPGA
- 这是一篇很精彩的硕士论文，里面详细论述了RS编译码的原理和实现方法，值得下载-This is a wonderful master rs decode thesis, which discusses in detail the RS encoding and decoding of the principle and method, it is worth to download! ! !
RS3123
- Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its ra
RS
- 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
rs-232vhdl
- it is the code for doing interfacing between computer and fpga board through rs-232.
基于FPGA的串口通信系统
- 该设计是基于 FPGA 的串口通信系统模拟仿真，通过对 RS-232 串行总线 接口的设计，掌握发送与接收电路的基本思路，并进行串口通信。采用 Verilog HDL 语言对 UART 波特率产生模块、数据发送模块、接收模块进行硬件描述， 再将其整合为一个 RS-232 收发模块，最终在顶层模块中将两个 RS-232 模块例 化，实现两块 FPGA 芯片全双工通信的设计。(Design of serial communication system based on FPGA)